View MC145532_11101.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC145532/D
ADPCM Transcoder
MC145532
16 1
Conforms to G.721-1988 and T1.301-1987
The MC145532 Adaptive Differential Pulse Code Modulation (ADPCM) Transcoder provides a low-cost, full-duplex, single-channel transcoder to (from) a 64 kbps PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or 64 kbps channel. * * * * * * * * * * * * * Complies with CCITT Recommendation G.721-1988 Complies with the American National Standard (T1.301-1987) Full-Duplex, Single-Channel Operation Mu-Law or A-Law Coding is Pin Selectable Synchronous or Asynchronous Operation Easily Interfaces with Any Member of Motorola's PCM Codec-Filter Mono-Circuit Family or Other Industry Standard Codec Serial PCM and ADPCM Data Transfer Rate from 64 kbps to 5.12 Mbps Power-Down Capability for Low Current Consumption The Reset State, an Option Specified in the Standards, is Automatically Initiated When the RESET Pin is Released Simple Time Slot Assignment Timing for Transcoder Applications Single 5 V Power Supply 16-Pin Package The MC145536EVK is the Evaluation Platform for the MC145532 and Also Includes the MC145480 5 V PCM Codec-Filter
DW SUFFIX SOG PACKAGE CASE 751G
16 1
L SUFFIX CERAMIC PACKAGE CASE 620
ORDERING INFORMATION
MC145532DW SOG Package MC145532L Ceramic Package
PIN ASSIGNMENT
MODE DDO DOE DDC DDI DIE RESET VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD EDO EOE EDC EDI EIE SPC APD
BLOCK DIAGRAM
DDO DOE S REG DDC DDI DIGITAL SIGNAL PROCESSOR REG LATCH S REG EDC EDI I/O DATA BUS EDO EDE
S REG DIE
LATCH
REG
S REG EIE
MODE APD VSS
RESET SPC VDD
REV 1 9/95 (Replaces NP470)
(c) Motorola, Inc. 1995 MOTOROLA
MC145532 1
DEVICE DESCRIPTION
An Adaptive Differential PCM (ADPCM) transcoder is used to reduce the data rate required to transmit a PCM encoded voice signal while maintaining the voice fidelity and intelligibility of the PCM signal. The transcoder is used on 64 kbps data streams which represent either voice or voice band data signals that have been digitized by a codec (e.g., MC145557). The transcoder uses a filter to attempt to predict the next PCM input value based on previous PCM input values. The error between the predicted and the true PCM input value is the information that is sent to the other end of the line. Hence the word differential, since the ADPCM data stream is the difference between the true PCM input value and the predicted value. The term "adaptive" applies to the filter that is performing the prediction. It is adaptive in that its transfer function changes based on the PCM input data. That is, it adapts to the statistics of the signals presented to it.
DECODER INPUT DDI Decoder Data Input (Pin 5) ADPCM data to be decoded are applied to this input pin, which operates in conjunction with DDC and DIE to enter the data in a serial format. DDC Decoder Data Clock (Pin 4) Data applied to DDI are latched into the transcoder on the falling edge of DDC and data are output from DDO on the rising edge of DDC. The frequency of DDC may be as low as 64 kHz or as high as 5.12 MHz. DIE Decoder Input Enable (Pin 6) The beginning of a new ADPCM word is indicated by a rising edge applied to this input. Data are serially clocked into DDI on the subsequent falling edges of DDC following the DIE rising edge. The frequency of DIE may not exceed 8 kHz. DECODER OUTPUT DDO Decoder Data Output (Pin 2) PCM data are available in a serial format from this output, which operates in conjunction with DDC and DOE. DDO is a three-state output that remains at a high-impedance state except when presenting data. DOE Decoder Output Enable (Pin 3) Each ADPCM word is requested by a rising edge on this input which causes the DDO pin to provide the data when clocked by DDC. One DOE must occur for each DIE. CONTEXT
PIN DESCRIPTIONS
ENCODER INPUT EDI Encoder Data Input (Pin 12) PCM data to be encoded are applied to this input pin which operates synchronously with EDC and EIE to enter the data in a serial format. EDC Encoder Data Clock (Pin 13) Data applied to EDI are latched into the transcoder on a falling edge of EDC and data are output from EDO on a rising edge of this input pin. The frequency of EDC may be as low as 64 kHz or as high as 5.12 MHz. EIE Encoder Input Enable (Pin 11) The beginning of a new PCM word is indicated to the transcoder by a rising edge applied to this input. The frequency of EIE may not exceed 8 kHz. ENCODER OUTPUT EDO Encoder Data Output (Pin 15) ADPCM data are available in a serial format from this output, which operates synchronously with EDC and EOE. EDO is a three-state output which remains in a high-impedance state, except when presenting data. EOE Encoder Output Enable (Pin 14) Each ADPCM word is requested by a rising edge on this input, which causes the EDO pin to provide the data when clocked by EDC. One EOE must occur for each EIE.
MODE Mode Select (Pin 1) A logic 0 applied to this input makes the transcoder compatible with Mu-255 companding and D3 data format. A logic 1 applied to this pin makes the transcoder compatible with A-Law companding with even bit inversion data format. SPC Signal Processor Clock (Pin 10) This input is typically clocked with a 20.48 MHz clock signal which is used as the digital signal processor master clock. This pin has a CMOS compatible input. RESET Reset (Pin 7) A logic 0 applied to this input forces the transcoder into a low power dissipation mode. A rising edge on this pin causes power to be restored and the optional transcoder RESET state (specified in the standards) to be forced. Valid data is available at the output pins four input enables after a rising edge on this pin. This pin has a CMOS compatible input.
MC145532 2
MOTOROLA
APD Absolute Power Down (Pin 9) A logic 1 applied to this input forces the transcoder into a power saving mode. This pin has a CMOS compatible input. POWER SUPPLY VDD Positive Power Supply (Pin 16) The most positive power supply pin, normally 5 V. VSS Negative Power Supply (Pin 8) The most negative power supply pin, normally 0 V.
Note that only a 32 kbps encoding rate can be specified when using short frame mode on the encoder input. ENCODER INPUT -- LONG FRAME Figure 2 shows the clock, enable, and data signals for the encoder input in long frame mode. In this mode, the data is captured by the MC145532 on the falling edge of EDC. The determination of the encoding rate is made based on the number of falling EDC edges seen by the MC145532 while EIE is high. Four edges implies a 32 kbps encoding rate, three edges implies a 24 kbps encoding rate, two edges implies a 16 kbps rate, and from five to eight inclusive imply a 64 kbps rate. The encoding rate may be changed on a frame-by-frame basis. The encoded word is available at EDO (via EOE and EDC) from 250 s to 375 s after it is requested. ENCODER OUTPUT -- SHORT FRAME Figure 3 shows the timing of the encoder output in short frame mode. The length of the LSB is always one half of an EDC cycle. The EDO will provide the correct number of bits for the encoding rate that was selected for this frame of data on the encoder input pins. The data is loaded into the MC145532 during one frame, encoded on the next frame, and read during the third frame. ENCODER OUTPUT -- LONG FRAME Figure 4 shows the timing of the encoder output in long frame mode. The enable must be wider than two falling edges of the EDC to be in long frame mode. If the enable falls before the correct number of bits have been presented to the output (EDO), the transcoder will complete the presentation of the bits to the output with the LSB being one half of an EDC period wide. If the enable falls after the one half EDC period of the LSB, then the LSB will be extended up to the full EDC clock period and the subsequent data will be a recirculation of the previous data, which repeats until the enable pin falls. This is shown on the second enable for the 16 kbps encoding rate example in Figure 4. DECODER INPUT -- SHORT FRAME Figure 5 shows the timing of the decoder data clock, the decoder input enable, and the decoder data input pins in short frame operation. Note that in this mode only a 32 kbps decoding rate can be selected. DECODER INPUT -- LONG FRAME Figure 6 shows the clock, enable, and data signals for the decoder input in long frame mode. The determination of the decoding rate is made based on the number of falling DDC edges seen by the MC145532 while DIE is high. Four edges implies a 32 kbps decoding rate, three edges implies a 24 kbps decoding rate, two edges implies a 16 kbps rate, and from five to eight edges inclusive imply a 64 kbps rate. The decoding rate may be changed on a frame-by-frame basis.
FUNCTIONAL DESCRIPTION
ENCODING/DECODING RATES The MC145532 allows for the encoding and decoding of data at one of four rates on a sample-by-sample basis. Each data sample that is provided to the part is accompanied by an indication of the rate at which it is to be encoded or decoded. The width of the enable pulse determines the encoding/decoding rate chosen for each sample. The 64 kbps rate allows for PCM data to be passed directly through the part. The 32 kbps rate is either the G.721-1988 or the T1.301-1987 standard, depending on the state of the mode pin. The 24 kbps encoding rate is compliant with CCITT G.723-1988 and G.726. The 16 kbps rate is a modified quantizer from the 32 kbps technique and is not a standard. TIMING Figures 1 through 8 show the timing of the input and output pins. The MC145532 determines the mode of the timing signals, either short or long frame, for each enable, independent of the mode of any previous enables. A transition from short frame to long frame mode or vice versa will cause at least one frame of data to be destroyed. Each of the four sets of I/O pins determines its mode independent of the other sets. Thus the encoder input could be operating with long frame timing and the output could be operating with short frame timing. Note that the short frame timing on the input enables can only be used with the 32 kbps transcoding rate. The number of data clock falling edges enclosed by the input enable line (EIE or DIE) determines both the short frame or long frame mode and the transcoding rate. The mode of the input or output is determined each frame. In all modes, the data is captured by the MC145532 on the falling edge of either EDC or DDC. ENCODER INPUT -- SHORT FRAME Figure 1 shows the timing of the encoder data clock (EDC), the encoder input enable (EIE), and the encoder data input (EDI) pins in short frame operation. The determination of short frame mode is made by the MC145532 based on one falling EDC edge while EIE is high.
MOTOROLA
MC145532 3
DECODER OUTPUT -- SHORT FRAME Figure 7 shows the timing of the decoder output in short frame mode. The DDO will provide the 8-bit PCM word for the decoding rate that was selected for this frame of data on the decoder input pins. The data is loaded into the MC145532 during one frame, decoded on the next frame, and read during the third frame. DECODER OUTPUT -- LONG FRAME Figure 8 shows the timing of the decoder output in long frame mode. Note that at least eight bits are presented to the output, provided that at least two falling edges of DDC are
seen while DOE is high. The enable can be used to extend the LSB to a full DDC period and/or cause the eight bits of data to be recirculated to the output pin until the enable falls. STANDARDS INFORMATION The following standards apply to the MC145532: T1.301-1987 -- 32 kbps ADPCM T1.303-1988 -- 24 kbps ADPCM CCITT G.721-1988, G.723-1988, and G.726 -- 32 kbps and 24 kbps CCITT, ITU-T, TIA, and EIA documents may be obtained by contacting Global Engineering Documents in the USA at (800) 854-7179, or internationally at (303) 397-7956.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating DC Supply Voltage Voltage, Any Pin to VSS DC Current, Any Pin Operating Temperature Storage Temperature Symbol VDD V Iin TA Tstg Value - 0.5 to + 7.0 - 0.5 to VDD + 0.5 10 - 40 to + 85 - 85 to + 150 Unit V V mA C C This device contains circuitry to protect against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
RECOMMENDED OPERATING CONDITIONS (TA = - 40 to + 85C)
Parameter DC Supply Voltage Power Dissipation Symbol VDD PD Min 4.50 -- Max 5.50 0.28 Unit V W
DIGITAL CHARACTERISTICS (VDD = 5.0 V, TA = - 40 to + 85C)
Parameter High Level Input Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance High Level Output Voltage (IOH = - 2.0 mA) Low Level Output Voltage (IOL = 2.0 MA) Output Leakage Current (VDD = 5.5 V) DDO, EDO DDO, EDO DDO, EDO Mode, DOE, DDC, DDI, DIE, EIE, EDI, EDC, EOE Mode, DOE, DDC, DDI, DIE, EIE, EDI, EDC, EOE RESET, APD, SPC RESET, APD, SPC Symbol VIH VIL VIH VIL Iin Cin VOH VOL Ilkg Min 2.0 -- 0.7 VDD -- -- -- 4.6 -- -- Max -- 0.8 -- 0.3 VDD 1.0 10 -- 0.4 5.0 Unit V V V V A pF V V A
SWITCHING CHARACTERISTICS (VDD = 5.0 V, TA = - 40 to + 85C)
Parameter SPC Frequency SPC Duty Cycle Min 19.990 45 Max 23 55 Unit MHz %
MC145532 4
MOTOROLA
ENCODER INPUT -- SHORT FRAME (VDD = 5.0 V, TA = - 40 to + 85C)
Parameter Enable Low Setup Time Enable Low Hold Time Enable Valid Time Enable Hold Time Data Valid Time Data Hold Time Symbol tsu(EIE)L th(EIE)H tV(EIE) th(EIE) tv(EDI) th(EDI) Min 15 30 15 15 15 15 Max -- -- -- -- -- -- Unit ns ns ns ns ns ns
EDC
1
2
3
4
5
6
7
8
EIE LSB EDI MSB MSB LSB
EDC th(EIE)H EIE th(EIE) tv(EIE) tsu(EIE)L
EDI tv(EDI)
MSB th(EDI)
Figure 1. Encoder Input Timing -- Short Frame
MOTOROLA
MC145532 5
ENCODER INPUT -- LONG FRAME (VDD = 5.0 V, TA = - 40 to + 85C)
Parameter Enable Low Hold Time Enable Valid Time Data Valid Time Data Hold Time Symbol th(EIE)L tv(EIE) tv(EDI) th(EDI) Min 30 15 15 15 Max -- -- -- -- Unit ns ns ns ns
EDC
1
2
3
4
5
6
7
8
EIE 32 kbps
EIE 24 kbps
EIE 16 kbps
EIE 64 kbps LSB EDI MSB MSB LSB
EDC th(EIE)L EIE th(EDI) tv(EDI) EDI MSB tv(EIE)
Figure 2. Encoder Input Timing -- Long Frame
MC145532 6
MOTOROLA
ENCODER OUTPUT -- SHORT FRAME (VDD = 5.0 V, TA = - 40 to + 85C)
Parameter Enable Low Hold Time Enable Valid Time Enable Hold Time Data Valid Time Data Three-State Time (with 150 pF Load) Symbol th(EOE)L tv(EOE) th(EOE) tv(EDO) tz(EDO) Min 30 15 15 -- 1 Max -- -- -- 40 30 Unit ns ns ns ns ns
EDC
1
2
3
4
5
6
7
8
EOE
*
LSB MSB
@ LSB MSB @ 64 kbps transcoding rate selected for this frame at EIE
EDO
* 32 kbps transcoding rate selected for this frame at EIE
EDC th(EOE)L EOE tx(EDO) tv(EDO) EDO MSB LSB tv(EOE) th(EOE)
Figure 3. Encoder Output Timing -- Short Frame
MOTOROLA
MC145532 7
ENCODER OUTPUT -- LONG FRAME (VDD = 5.0 V, TA = - 40 to + 85C)
Parameter Enable Low Hold Time Enable Valid Time Enable to Data Time (Whichever Edge Occurs Last) Clock to Data Time (Whichever Edge Occurs Last) Symbol th(EOE)L tv(EOE) tEOE-EDO tEDC-EDO Min 30 15 -- -- Max -- -- 40 45 Unit ns ns ns ns
EDC
1
2
3
4
5
6
7
8
EOE 32 kbps EDO MSB LSB MSB
* *
EOE 24 kbps EDO MSB MSB #
EOE 16 kbps EDO MSB MSB MSB
@
MSB
EOE 64 kbps EDO MSB * EDO Driver is controlled by EOE # EDO completes the presentation of data @ Data recirculates MSB
EDC th(EOE)L EOE tEOE-EDO tEDC-EDO EDO MSB tv(EOE)
Figure 4. Encoder Output Timing -- Long Frame
MC145532 8
MOTOROLA
DECODER INPUT -- SHORT FRAME (VDD = 5.0 V, TA = - 40 to + 85C)
Parameter Enable Low Setup Time to Falling DDC Enable Low Hold Time from Falling DDC Enable Valid Time to Falling DDC Enable Hold Time from Falling DDC Data Valid Time Before Falling DDC Data Hold Time from Falling DDC Symbol tsu(DIE)L th(DIE)H tv(DIE) th(DIE) tv(DDI) th(DDI) Min 15 30 15 15 15 15 Max -- -- -- -- -- -- Unit ns ns ns ns ns ns
DDC
1
2
3
4
5
6
7
8
DIE
DDI
MSB
MSB
1 DDC th(DIE)H DIE tv(DDI) DDI MSB th(DDI) tv(DIE) th(DIE) tsu(DIE)L
2
Figure 5. Decoder Input Timing -- Short Frame
MOTOROLA
MC145532 9
DECODER INPUT -- LONG FRAME (VDD = 5.0 V, TA = - 40 to + 85C)
Parameter Enable Hold Time from Falling DDC Enable Valid Time to Falling DDC Data Valid Time to Falling DDC Data Hold Time from Falling DDC Symbol th(DIE) tv(DIE) tv(DDI) th(DDI) Min 30 15 15 15 Max -- -- -- -- Unit ns ns ns ns
DDC
1
2
3
4
5
6
7
8
DIE 32 kbps DDI MSB LSB MSB
DIE 24 kbps DDI MSB MSB
DIE 16 kbps DDI MSB MSB
DIE 64 kbps DDI MSB MSB
DDC th(DIE) DIE tv(DDI) DDI MSB th(DDI) tv(DIE)
Figure 6. Decoder Input Timing -- Long Frame
MC145532 10
MOTOROLA
DECODER OUTPUT -- SHORT FRAME (VDD = 5.0 V, TA = - 40 to + 85C)
Parameter Enable Low Hold Time Enable Valid Time Enable Hold Time Rising Edge of DDC to Valid DDO Delay Time from 8th DDC Low to DDO Output Disabled Symbol th(DOE)L tv(DOE) th(DOE) tv(DDO) tz(DDO) Min 30 15 15 -- -- Max -- -- -- 40 30 Unit ns ns ns ns ns
DDC
1
2
3
4
5
6
7
8
DOE LSB DDO MSB MSB LSB
DDC th(DOE)L DOE tz(DDO) tv(DDO) DDO MSB LSB tv(DOE) th(DOE)
Figure 7. Decoder Output Timing -- Short Frame
MOTOROLA
MC145532 11
DECODER OUTPUT -- LONG FRAME (VDD = 5.0 V, TA = - 40 to + 85C)
Parameter Enable Low Hold Time Enable Valid Time Rising Edge of DDE to Valid DDO (When DDC is High) Rising Edge of DDC to Valid DDO (When DOE is High) Delay Time from 8th DDC Low or DOE Low to DDO Output Disabled Symbol th(DOE)L tv(DOE) tDOE-DDO tDDC-DDO tz(DDO) Min 30 15 -- -- 0 Max -- -- 40 45 30 Unit ns ns ns ns ns
DDC
1
2
3
4
5
6
7
8
DOE
DDO
MSB
MSB
DDC th(DOE)L DOE tDOE-DDO tDDC-DDO DDO MSB tv(DOE)
Figure 8. Decoder Output Timing -- Long Frame
MC145532 12
MOTOROLA
MC145532 PCM Y BUS OUT TS 1 ADPCM Z BUS IN TS 3 MODE DDO DOE DDC DDI DIE RESET VSS VDD EDO EOE EDC EDI EIE SPC APD +5V ADPCM Z BUS OUT TS 1 PCM Y BUS IN TS 3
1.544 MHz
PCM X BUS OUT TS 3
MODE DDO DOE DDC
MC145532 VDD EDO EOE EDC EDI EIE SPC APD
+5V TS 2 PCM X BUS IN TS 1 20.48 MHz
TS 4 POWER-DOWN
DDI DIE RESET VSS
1.544 MHz
TS 1 TS 2
TS 3
TS 4
PCM BUS OUT
DDO y
1
2
3
4
5
6
7
8 1 2
DDO x
3
4
5
6
7
8
PCM BUS IN
EDI y EDI x 1 2 3 4 5 6 7 8
1
2
3
4
5
6
7
8
ADPCM BUS OUT EDO zy
1
2
3
4
EDO zx ADPCM BUS IN DDI zy DDI zx
1
2
3
4
1
2
3
4
Figure 9. ADPCM Transcoder Application
MOTOROLA
MC145532 13
MC145503 ANALOG OUT ANALOG IN VAG RxO +Tx Txl -Tx +5V -5V Mu/A PDI VSS VDD RDD RCE RDC TDC TDD TDE VLS +5V
ADPCM IN DDO TSm1 TSm DOE DDC DDI DIE
MC145532 MODE VDD EDO EOE EDC EDI EIE SPC APD +5V ADPCM OUT TSm 1.544 MHz
RESET VSS
20.48 MHz
POWER-DOWN
1.544 MHz = RDC = DDC = TDE = EDC TSm1 = RCE = TDE EDI = TDD TSm = EIE = EOE = DIE = DOE ADPCM OUT = EDO
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
DDO = RDD
1
2
3
4
5
6
7
8
ADPCM IN = DDI
1
2
3
4
Figure 10. ADPCM Transcoder/Codec Application
MC145532 14
MOTOROLA
MC145557 -5V ANALOG OUT +5V VBB GNDA VFRO VCC FSR DR BCLKR MCLKR VFXI+ VFXI- GSX TSX FSX DX BCLKX MCLKX 8 kHz +5V ADPCM OUT ANALOG IN Tx TIME SLOT
+5V
MC145532 VDD MODE DDO DOE DDC DDI DIE RESET VSS EDO EOE EDC EDI EIE SPC APD
2.048 MHz ADPCM IN POWER-DOWN
20.48 MHz
2.048 MHz = MCLKR = BCLKR = DDC = MCLKX = BCLKX = EDC 8 kHz = DOE = DIE = FSR = EOE = EIE = FSX EDI = DX
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
ADPCM OUT = EDO
1
2
3
4
DDO = DR
1
2
3
4
5
6
7
8
ADPCM IN = DDI
1
2
3
4
Figure 11. ADPCM Transcoder/Codec Application (A-Law)
MOTOROLA
MC145532 15
PACKAGE DIMENSIONS
DW SUFFIX SOG PACKAGE CASE 751G-02
9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
-A-
16
-B-
1 8
8X
P 0.010 (0.25)
M
B
M
16X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45 _ C -T-
14X DIM A B C D F G J K M P R
G
K
SEATING PLANE
M
L SUFFIX CERAMIC PACKAGE CASE 620-09 -A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.770 0.240 0.290 -- 0.165 0.015 0.021 0.050 BSC 0.055 0.070 0.100 BSC 0.009 0.011 -- 0.200 0.300 BSC 0 15 0.015 0.035 MILLIMETERS MIN MAX 19.05 19.55 7.36 6.10 4.19 -- 0.53 0.39 1.27 BSC 1.77 1.40 2.54 BSC 0.27 0.23 5.08 -- 7.62 BSC 15 0 0.39 0.88
-B1 8
C
L
-TSEATING PLANE
K E F G D 16 PL 0.25 (0.010)
M
N
M J 16 PL 0.25 (0.010)
M
TB
S
DIM A B C D E F G J K L M N
TA
S
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MC145532 16
*MC145532/D*
MC145532/D MOTOROLA

▲Up To Search▲

Price & Availability of MC145532

	To Download MC145532 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .